ELEMENTS OF DIGITAL ELECTRONICS AND SIGNAL PROCESSING
ELEMENTS OF DIGITAL ELECTRONICS AND SIGNAL PROCESSING
Abstract and Keywords
This chapter first describes logic functions and illustrates how false signals are formed due to timing errors. Basic logic circuits are described (NMOS, PMOS, CMOS) together with propagation delays and power dissipation. The application of logic circuitry in analogtodigital converters is illustrated, with a detailed discussion of conversion flaws (channel profile, integral and differential nonlinearity, rate dependence). Different types of analogtodigital converters are described (flash, successive approximation, Wilkinson, and pipelined ADCs) with their strengths and shortcomings. The chapter closes with a brief discussion of sampling, the Nyquist criterion, and digital signal processing.
Keywords: logic functions, propagation delay, logic power dissipation, analogtodigital converters, channel profile, integral nonlinearity, differential nonlinearity, rate dependence, digital signal processing, Nyquist criterion
5.1 Digital circuit elements
The basic difference between analog and digital signals is illustrated in Figure 5.1. Analog signals utilize continuously variable properties of the pulse to impart information, such as the pulse amplitude or pulse shape. Digital signals have constant amplitude, but the presence of the signal at specific times is evaluated, i.e. whether the signal is in one of two states, “low” or “high”. However this still involves an analog process, as the presence of a signal is determined by the signal level exceeding a threshold.
Shannon (1949) described the transmission capacity of a digital link (bits per second):
5.1.1 Logic elements
Figure 5.2 illustrates several functions utilized in digital circuits (“logic” functions). An AND gate provides an output only when all inputs are high. An OR gives an output when any input is high. An eXclusive OR (XOR) responds when only one input is high. The same elements are commonly implemented with inverted outputs, then called NAND and NOR gates, for example. The D flipflop
Logic circuits are fundamentally amplifiers, so they also suffer from bandwidth limitations. The pulse train of the AND gate in Figure 5.2 illustrates a common problem. The third pulse of input B is going low at the same time that input A is going high. Depending on the time overlap, this can yield a narrow output that may or may not be recognized by the following circuit. In an EXOR this can occur when two pulses arrive nearly at the same time. The D flipflop requires a minimum setup time for a level change at the D input to be recognized, so changes in the data level may not be recognized at the correct time. The probability of these marginal events may be extremely rare and perhaps go unnoticed. Data transmission protocols have been developed to detect such errors (parity checks, Hamming codes, etc.), so corrupted data can be rejected. However, in complex systems the combination of “glitches” can make the system “hang up”, necessitating a system reset.
Some key aspects of logic systems can be understood by inspecting the circuit elements that are used to form logic functions. Figure 5.4 shows simple inverter circuits using MOS transistors. These devices will be described in the next chapter. At this point it is sufficient to know that in an NMOS transistor a conductive (p.193)
5.1.2 Propagation delays and power dissipation
Logic elements always operate in conjunction with other circuits, as illustrated in Figure 5.6. The wiring resistance in conjunction with the total load capacitance increases the rise time of the logic pulse and as a result delays the time when
Fast logic is timecritical. It relies on logic operations from multiple paths coming together at the right time. Valid results depend on maintaining minimum allowable overlaps (e.g. AND) and setup times (latches). Each logic circuit has a finite propagation delay, which depends on circuit loading, i.e. how many loads the circuit has to drive. In addition, as illustrated in Figure 5.6 the wiring resistance and capacitive loads introduces delay. This depends on the number of circuits connected to a wire or trace, the length of the trace and the dielectric constant of the substrate material. Relying on control of circuit and wiring delays to maintain timing requires great care, as it depends on circuit variations and temperature. In principle all of this can be simulated, but in complex systems there are too many combinations to test every one. A more robust solution is to use synchronous systems, where the timing of all transitions is determined by a master clock. Generally, this does not provide the utmost speed and requires some additional circuitry, but increases reliability. Nevertheless, clever designers frequently utilize asynchronous logic. Sometimes it succeeds … and sometimes it doesn't.
5.1.3 Logic arrays
Commodity integrated circuits with basic logic blocks are readily available, e.g. with four NAND gates or two flipflops in one package. These can be combined to form simple digital systems. However, complex logic systems are no longer designed using individual gates. Instead, logic functions are described in a highlevel language (e.g. VHDL), synthesized using design libraries, and implemented as custom ICs – “ASICs” (application specific ICs) – or programmable logic arrays. In these implementations the digital circuitry no longer appears as an (p.196)
5.2 Digitization of pulse height and time
For data storage and subsequent analysis the analog signal at the shaper output must be digitized. Important parameters for analogtodigital converters (ADCs or A/Ds) used in detector systems are:

1. Resolution: The “granularity” of the digitized output.

2. Differential nonlinearity: How uniform are the digitization increments?

3. Integral nonlinearity: How much does the relationship of the digital output to the analog input deviate from strict proportionality?

4. Conversion time: How much time is required to convert an analog signal to a digital output?

5. Countrate performance: How quickly can a new conversion commence after completion of a prior one without introducing deleterious artifacts?

6. Stability: Do the conversion parameters change with time?
Instrumentation ADCs used in industrial data acquisition and control systems share most of these requirements. However, detector systems place greater emphasis on differential nonlinearity and countrate performance. The latter is important, as detector signals often occur randomly, in contrast to systems where signals are sampled at regular intervals. As in amplifiers, if the DC gain is not precisely equal to the highfrequency gain, the baseline will shift. Furthermore, following each pulse it takes some time for the baseline to return to its quiescent level. For periodic signals of roughly equal amplitude these baseline deviations (p.197) will be the same for each pulse, but for a random sequence of pulse with varying amplitudes, the instantaneous baseline level will be different for each pulse and affect the peak amplitude.
5.2.1 ADC parameters
5.2.1.1 Digitizer resolution
Digitization incurs approximation, as a continuous signal distribution is transformed into a discrete set of values. To reduce the additional errors (noise) introduced by digitization, the discrete digital steps must correspond to a sufficiently small analog increment. For an accurate measurement, the resolution of the ADC must be significantly better than the noise level of the signal. Since pulse amplitudes varying within the digitization interval ΔV yield the same digitization result, the rms error
Another consideration is settling time. Given a single pole response V(t) = V _{0} exp(−t/τ), for a given precision ΔV/V _{0} the settling time t = − τ log (ΔV/V _{0}). To achieve a precision of 10^{−4} one must wait 9.2τ before acquiring the signal.
Apart from these considerations, the simplistic assumption is that the number of output bits n determines the digitizer resolution, ΔV = V/2^{n}. For example, 13 bits yield ΔV/V = 1/8192 = 1.2 · 10^{−4}.
If we plot the probability vs. pulse amplitude that a pulse height corresponding to a specific output bin is actually converted to that address or bin, an ideal ADC would show the response illustrated in Figure 5.8. In reality, the channel profile is not rectangular as sketched above. Assigning analog amplitudes to digital bins involves a threshold comparator. As in every amplitude measurement,
These channel profiles were measured by scanning a precision pulser across a channel and recording the fraction of pulses converted into the proper digital bin. However, channel profile can be checked quickly by applying the output of a precision pulser to the ADC and carefully adjusting the output amplitude to the center of a digital bin. If the pulser output has very low noise, i.e. the amplitude jitter is much smaller than the voltage increment corresponding to one ADC channel, nearly all pulses will be converted to a single channel, with only a small fraction appearing in the neighbor channels. However, this is only true for welldesigned ADCs. Figure 5.11 shows results from an ADC whose digital resolution is better than its analog resolution. In the 13bit range the pulser
How much ADC resolution is required? If all counts of a peak fall in one bin, the resolution is ΔV. If the counts are distributed over several bins, peak fitting can yield substantially better resolution, depending on statistics. Figure 5.12 shows a signal with a constant width digitized with bin widths of ΔV = 2σ, σ, 0.5σ, and 0.25σ. Fitting can determine the centroid position to a fraction of the bin width even with coarse digitization, if only one peak is present and the line shape is known. Five digitizing channels within a linewidth (FWHM) allow robust peak fitting and centroid finding, even for imperfectly known line shapes and overlapping peaks.
5.2.1.2 Differential nonlinearity
Differential nonlinearity (DNL) is a measure of the uniformity of channel profiles over the range of the ADC. Depending on the nature of the distribution, either a peak or an rms specification may be appropriate:
Differential nonlinearity of < ± 1% max. is typical, but stateoftheart ADCs can achieve 10^{−3} rms, i.e. the variation is comparable to the statistical fluctuation for 10^{6} random counts. Instrumentation ADCs are often specified with an (p.200)
5.2.1.3 Integral nonlinearity
Integral nonlinearity measures the deviation from proportionality of the measured amplitude to the input signal level. Figure 5.14 shows the channel number vs. input amplitude and the deviation of the output from a straightline fit.
The linearity of an ADC depends on the input pulse shape and duration, due to bandwidth limitations in the circuitry. The integral nonlinearity shown above
5.2.1.4 Conversion time
During the digitization of a signal the system cannot accept a subsequent signal (“dead time”). The dead time results from several successive steps in the conversion process:

1. Signal acquisition time, which equals the timetopeak plus settling time.

2. Conversion time, which can depend on pulse height.

3. Readout time to memory, which depends on speed of data transmission, buffer memory access and writing to mass storage.
In pulsed beam experiments dead time can be ignored if it is smaller than the pulse rate, so that conversion and data storage are complete before the next event. However, in continuous event streams, unless the event rate is very low, the measurement of yields or reaction crosssections requires a measurement of dead time, e.g. with a reference pulser fed simultaneously into the spectrum. The total number of reference pulses issued during the measurement is counted and compared with the number of pulses recorded in the spectrum.
As will be seen below, the conversion time can depend on the pulse height. Does this mean that the efficiency is a function of pulse height? Usually not. If events in different parts of the spectrum are not correlated in time, i.e. random, they are all subject to the same average dead time (although this average will depend on the spectral distribution). However, be cautious when events are correlated. For example, in decay chains where the lifetime is less than the dead time, the daughter decay will be lost systematically.
5.2.1.5 Count rate effects
Circuitry in ADCs is mostly analog, so as in amplifiers one often encounters internal baseline shifts with event rate or undershoots following a pulse. If signals occur at constant intervals, the effect of an undershoot
5.2.1.6 Stability
The conversion gain and baseline are subject to change with time and temperature. Stability vs. temperature is usually adequate with modern electronics in a laboratory environment, especially since temperature changes within an enclosure or integrated circuit are typically much smaller than ambient changes. However, in highly precise or longterm measurements one should monitor changes in gain and baseline of the overall system. A simple technique is to inject precision reference pulses to place a reference peak at both the low and high end of the spectrum. The difference between the two peaks yields the gain, and the position of either peak then determines the offset.
5.2.2 Analogtodigital conversion techniques
Analogtodigital converters suitable for the digitization of individual pulses tend to use variations of a few basic techniques. Here we just review some basic conversion principles to illustrate the strengths and weaknesses of different conversion techniques. Analogtodigital converters are key components in many applications, so a wealth of literature can be found on the world wide web. Application
5.2.2.1 Flash ADC
Conceptually, the simplest technique is flash conversion, illustrated in Figure 5.17. The signal is fed in parallel to a bank of threshold comparators. The individual threshold levels are set by a resistive divider. The comparator outputs are encoded such that the output of the highest level comparator that fires yields the correct bit pattern. The threshold levels can be set to provide a linear conversion characteristic where each bit corresponds to the same analog increment, or a nonlinear characteristic, to provide increments proportional to the absolute level, which provides constant relative resolution over the range.
The big advantage of this scheme is speed; conversion proceeds in one step and conversion times < 10 ns are readily achievable. The drawbacks are component count and power consumption, as one comparator is required per bit. For example, an eightbit converter requires 256 comparators. The conversion is always monotonic and differential nonlinearity is determined by the matching of the resistors in the threshold divider. Only relative matching is required, so this topology is a good match for monolithic integrated circuits. Flash ADCs are available with conversion rates > 500 MS/s (megasamples per second) at eightbit resolution. The power dissipation is about 5 W. A practical issue is the high input capacitance of many comparator inputs in parallel, so the driver must have sufficient current drive capability to charge up this capacitance commensurate with the fast conversion time. The required settling time increases the conversion time at high resolution, as V = V _{0} (1 − e ^{− t/τ}), so for the signal to approach its peak value to a precision of 10^{−3} requires a time of seven time constants τ.
5.2.2.2 Successive approximation ADC
The most commonly used technique is the successive approximation ADC, shown in Figure 5.18. The input pulse is sent (p.205)
A common limitation is differential nonlinearity, since the resistors that set the DAC levels must be extremely accurate. For DNL < 1% the resistor determining the 2^{12} level in a 13bit ADC must be accurate to < 2.4 · 10^{−6}. As a consequence, differential nonlinearity in highresolution successive approximation converters is typically 10 – 20% and often exceeds the 0.5 LSB required to ensure monotonic response.
The differential nonlinearity can be corrected by various techniques. One is to average over many channel profiles for a given pulse amplitude, the “sliding scale” technique originated by Gatti (Cottini, Gatti, and Svelto 1963). Here an analog increment is added eventbyevent and the digitized output is corrected accordingly. Thus, for a large number of events the conversion of a given pulse amplitude utilizes many states of the converter. For a random amplitude distribution this averages over many channel profiles and equalizes the differential (p.206) nonlinearity. When properly implemented this provides excellent differential nonlinearity with no significant degradation of the channel profile. However, flawed implementations are prone to steplike discontinuities in the DNL vs. amplitude.
Another technique is the “brute force” approach of using a correction DAC. The primary DAC output is adjusted by the output of a correction DAC to reduce differential nonlinearity. This is shown in Figure 5.19. Correction data are derived from a measurement of DNL. Corrections for each bit are loaded into the RAM, which acts as a lookup table. For each address of the main DAC the appropriate correction is applied to the correction DAC. The range of the correction DAC must exceed the peaktopeak differential nonlinearity. If the correction DAC has N bits, the maximum DNL is reduced by 2^{−(N−1)} (if the deviations are symmetrical).
5.2.2.3 Wilkinson ADC
The Wilkinson ADC (Wilkinson 1950) has traditionally been the mainstay of precision pulse digitization. The principle is shown in Figure 5.20. The peak signal amplitude V is acquired by a combined peak detector/pulse stretcher and transferred to a memory capacitor. The output of the peak detector initiates the conversion process:

1. The memory capacitor is disconnected from the stretcher.

2. A current source is switched on to linearly discharge the capacitor with current I _{R}.

3. Simultaneously with commencing the discharge a counter is enabled to determine the number of clock pulses until the voltage on the capacitor reaches the baseline level V _{BL}.
The time required to discharge the capacitor is a linear function of pulse height,
Many important details are not shown in Figure 5.20. For example, the beginning of the discharge must be synchronized with the clock. Switching the current source requires some time, which introduces nonlinearity for small signals. Crosstalk from the clock or counter to the analog circuitry can introduce correlations into the differential nonlinearity, as illustrated in Figure 5.13. It is tempting to utilize both the leading and trailing edge of the clock pulse to double the clock frequency and reduce conversion time. However, the duty cycle of the clock pulse must be constrained very accurately to 50% to avoid degradation of differential nonlinearity. This technique typically leads to odd–even structures in the DNL, so the least significant bit can become unusable. Simply suppressing this bit also reduces the conversion time twofold, so “clock doubling” becomes selfdefeating.
5.2.2.4 Hybrid analogtodigital converters
Conversion techniques can be combined to obtain high resolution and short conversion time. One example combines a flash ADC with a successive approximation or a Wilkinson (ramp rundown) converter. The fast flash ADC provides coarse conversion (e.g. 8 out of 13 bits) and the successive approximation or Wilkinson converter provides fine resolution. Since the second conversion range is small, the conversion time is significantly reduced. For example, a Wilkinson ADC covering 256 channels with a 100 MHz clock requires only 2.6 µs, which is comparable to a successive approximation ADC, but with superior differential nonlinearity.
Another approach is to use flash ADCs with subranging. Not all applications require constant absolute resolution over the full range. Sometimes only relative (p.208)
Subranging utilizes a precision binary divider at the input to determine the coarse range and a fast flash ADC for fine digitization. One example is a fast digitizer that fits in phototube base and provides 17 to 18 bit dynamic range with 16 ns conversion time (Yarema et al. 1993, Zimmerman and Hoff 2004). The converter provides a digital floating point output (4 bit exponent, 8+1 bit mantissa).
A popular architecture is the pipelined ADC, which consists of sequential conversion steps, as illustrated in Figure 5.21. The input to each stage is fed both to a sample and hold and a threebit flash ADC. The sample and hold (S&H) maintains the signal level during conversion. The flash ADC quantizes its input to 3bit accuracy. This output is fed to a DAC with 12bit accuracy. The DAC's analog output is subtracted from the original signal and the difference signal is passed on to the next stage. The last 4 bits are resolved by a 4bit flash ADC. As soon as a stage has passed its result to the next stage it can begin processing the next signal, so throughput is not determined by the total conversion time, but by the time per stage. Since outputs from individual stages appear sequentially, the outputs must be aligned in time to form the cumulative digitized output. Since the interstage gain is only four (rather than eight corresponding to 3 bits), each stage only contributes 2 bits of resolution. The extra bit is used for error correction. Commercially available pipelined ADCs provide 1 GS/s conversion rates with eightbit resolution and a power dissipation of about 1.5 W. Note that (p.209)
Other techniques, the sigmadelta ADC being a notable example, measure incremental changes over the waveform. This architecture is popular in audio applications, so the frequencies are much lower than needed for the digitization of detector pulses.
5.3 Timetodigital converters (TDCs)
5.3.1 Counter
The combination of a clock generator with a counter is the simplest technique, shown in Figure 5.22. The clock pulses are counted between the start and stop signals, which yields a direct readout in real time. The limitation is the speed of the counter, which in current technology is limited to about 1 GHz, yielding a time resolution of 1 ns. Using the stop pulse to strobe the instantaneous counter status into a register provides multihit capability.
5.3.2 Analog ramp
Analog techniques are commonly used in highresolution digitizers to provide resolution in the range of ps to ns. The principle is to convert a time interval into a voltage by charging a capacitor through switchable current source. The start pulse turns on the current source and the stop pulse turns it off. The resulting voltage on the capacitor C is V = Q/C = I _{T} (t _{stop} − t _{start})/C, which is digitized by an ADC. A convenient implementation switches the current source to a smaller discharge current I _{R} and uses a Wilkinson ADC for digitization, as illustrated in Figure 5.23. This technique provides high resolution, but at the expense of dead time and multihit capability.
5.3.3 Digitizers with clock interpolation
Integrated circuit technology makes it practical to implement clock interpolation to provide ps resolution together with multihit capability and no dead time (p.210)
5.4 Digital signal processing
Up to now we have utilized analog techniques for pulse shaping. However, filtering can also be applied in the digital domain. This is a topic worthy of a book in itself, so this will only be a brief introduction designed to provide some perspective relevant to largescale detector systems. For a more detailed discussion of digital signal processing techniques see texts by Ifeachor and Jervis (1993), Oppenheimer and Schafer (1998), and others. For examples applied to detector pulse processing see Pullia et al. (2000) and Cardoso et al. (2004), which also give additional references.
First, the detector signal is sampled with a fast digitizer with sufficient resolution to reconstruct the pulse, as shown in Figure 5.25. Subsequently, a digital signal processor (DSP) applies the appropriate algorithms to filter the pulse and extract the pulse height (Figure 5.26). Digital signal processing allows great flexibility in implementing filtering functions. The software can be changed readily to adapt to a wide variety of operating conditions and it is possible to implement filters that are impractical or even impossible using analog circuitry. However, this comes at the expense of increased circuit complexity and increased demands on the ADC compared to analog shaping.
Figure 5.27 illustrates how a filter function can be implemented using digital techniques. The amplitude of the input signal is multiplied at each discrete time step by a filter weighting function. The filter function can be calculated in real time by the DSP or it can be stored as values in a lookup table. This process could be applied to either a continuous or a digitized input signal. Subsequently the samples are integrated. Since the amplitudes add coherently, whereas the noise components add in quadrature, this yields a net improvement in signaltonoise ratio. It is also rather straightforward to show that the optimum signaltonoise ratio obtains when the weighting function has the same shape as the input signal. This is an example of a “matched filter”. However this is only the optimum filter for retrieving the signal while retaining its shape. As we have seen, integrating the signal to extend its duration and then filtering decouples the choice of filter parameters from the original signal duration.
The simple scheme shown in Figure 5.27 requires that the time of the desired signals is known, so the weighting factors can be synchronized with the signal. This constraint is removed when the filtering is performed by convolution, so the DSP block in Figure 5.26 performs a sequence of multiplications and sums
The sample interval must be sufficiently small to capture the pulse structure. Figure 5.28 shows the same pulse as in Figure 5.25, but sampled at intervals of 4 ns instead of 1 ns. The sampling interval of 4 ns misses the initial peak.
This illustrates the Nyquist criterion. The ADC must digitize at greater than twice the rate of the highest frequency component in the signal. Apart from missing information on the fast components of the pulse, undersampling introduces spurious artifacts. With too low a sampling rate high frequency components will be “aliased” to lower frequencies, as shown in Figure 5.29.
To prevent aliasing, a lowpass filter must be introduced before the ADC. As a result, an additional analog block must be added to the signal processing chain (Figure 5.30). When an input frequency f _{i} is sampled at a rate f _{s}, the output frequencies can be reconstructed as f _{i} ± kf _{s}, where k is any integer value. Thus, the input is aliased to both lower and higher frequencies and the prefilter (“antialiasing filter”) is needed to exclude both possibilities. Every sampling process is subject to aliasing – e.g. also 2D or 3D image processing.
The preamplifier is necessary to raise the level of the input noise sources such that the digitization noise of the ADC is negligible. As already noted in Section 5.2.1.1, the signal quantization inherent to the digitization process introduces quasirandom noise
From this we see that the frontend electronics and ADC must exhibit the same precision as in an analog system, i.e. the baseline and other pulsetopulse amplitude fluctuations must be less than order Q _{n}/10, i.e. typically 10^{−4} in highresolution systems. For 10 V full scale at the ADC input in a highresolution gammaray detector system, this corresponds to < 1 mV. In practice the effective
Today digital signal processing is technically feasible for some applications, e.g. detectors with moderate to long collection times (gamma and xray detectors), and systems are commercially available. Nevertheless, these systems tend to be complex and powerhungry.
In largescale systems, however, the benefits are not so clear. Where intimate integration of sensors and electronics in a small volume is required, both circuit area and power dissipation are crucial considerations. Furthermore, these are special purpose systems. The electronics are specifically tailored to the sensor and application and do not need to be modified during the course of the experiments (the inevitable upgrades notwithstanding). Furthermore, simple analog filters usually provide results that are only slightly inferior to the optimized filters that a DSP system would allow.
The benefits of digital signal processing are:

1. Flexibility in implementing filter functions.

2. Filters are possible that are impractical in hardware.

3. Filter parameters can be changed simply.

4. Tail cancellation and pileup rejection are easily incorporated.

5. Adaptive filtering can be used to compensate for pulse shape variations.
Where is digital signal processing appropriate? It provides clear benefits in systems that are highly optimized for resolution, high counting rates, and variable sensor pulse shapes.
Where is analog signal processing best (most efficient)? In systems that require fast time response the high power requirements of highspeed ADCs are prohibitive. Systems that are not sensitive to pulse shape can use fixed shaper constants and rather simple filters, which can be either continuous or sampled. For example, the APV25 chip described in Chapter 8 applies discrete sample processing using analog circuitry. Finally, in high density systems that require small circuit area and low power, analog filtering can efficiently transpose the relevant information to a frequency domain where digitization requirements are less demanding.
Given the dearth of good analog circuit designers and no prospects for improvement, it is often claimed that digital signal processing is a better match to available skills and avoids the need to understand the wide range of details that a sophisticated analog system requires. This argument is specious; both types (p.216) of systems require careful analog design. Nevertheless, progress in fast ADCs (precision, reduced power) will expand the range of DSP applications.
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