## Helmuth Spieler

Print publication date: 2005

Print ISBN-13: 9780198527848

Published to Oxford Scholarship Online: September 2007

DOI: 10.1093/acprof:oso/9780198527848.001.0001

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# ELEMENTS OF DIGITAL ELECTRONICS AND SIGNAL PROCESSING

Chapter:
(p.191) 5 ELEMENTS OF DIGITAL ELECTRONICS AND SIGNAL PROCESSING
Source:
Semiconductor Detector Systems
Publisher:
Oxford University Press
DOI:10.1093/acprof:oso/9780198527848.003.0005

# Abstract and Keywords

This chapter first describes logic functions and illustrates how false signals are formed due to timing errors. Basic logic circuits are described (NMOS, PMOS, CMOS) together with propagation delays and power dissipation. The application of logic circuitry in analog-to-digital converters is illustrated, with a detailed discussion of conversion flaws (channel profile, integral and differential non-linearity, rate dependence). Different types of analog-to-digital converters are described (flash, successive approximation, Wilkinson, and pipelined ADCs) with their strengths and shortcomings. The chapter closes with a brief discussion of sampling, the Nyquist criterion, and digital signal processing.

# 5.1 Digital circuit elements

The basic difference between analog and digital signals is illustrated in Figure 5.1. Analog signals utilize continuously variable properties of the pulse to impart information, such as the pulse amplitude or pulse shape. Digital signals have constant amplitude, but the presence of the signal at specific times is evaluated, i.e. whether the signal is in one of two states, “low” or “high”. However this still involves an analog process, as the presence of a signal is determined by the signal level exceeding a threshold.

Shannon (1949) described the transmission capacity of a digital link (bits per second):

(5.1)
$Display mathematics$
where B is the bandwidth, S the signal (pulse amplitude), and N the noise. The noise enters, because near the switching threshold, digital elements are amplifiers. Although fundamentally limited by thermal noise as in analog circuits, the signal-to-noise ratio in digital systems is usually determined by cross-talk from other digital circuits. Thus, increasing the pulse amplitude will not improve the signal-to-noise ratio. Although digital systems are commonly described as a simple matter “yes” or “no”, real systems must also deal with “maybe”.

## 5.1.1 Logic elements

Figure 5.2 illustrates several functions utilized in digital circuits (“logic” functions). An AND gate provides an output only when all inputs are high. An OR gives an output when any input is high. An eXclusive OR (XOR) responds when only one input is high. The same elements are commonly implemented with inverted outputs, then called NAND and NOR gates, for example. The D flip-flop

Fig. 5.1 Analog signals contain information in the form of amplitude (left). Digital signals have a fixed amplitude. Information is carried in the time structure of a pulse train (right).

(p.192)

Fig. 5.2 Basic logic functions include gates (AND, OR, Exclusive OR) and flip flops.

is a bistable memory circuit that records the presence of a signal at the data input D at the time of a signal transition at the clock input CLK. This device is commonly called a latch. Inverted inputs and outputs are denoted by small circles or by superimposed bars, e.g. Q is the inverted output of a flip flop, as shown in Figure 5.3.

Logic circuits are fundamentally amplifiers, so they also suffer from bandwidth limitations. The pulse train of the AND gate in Figure 5.2 illustrates a common problem. The third pulse of input B is going low at the same time that input A is going high. Depending on the time overlap, this can yield a narrow output that may or may not be recognized by the following circuit. In an EX-OR this can occur when two pulses arrive nearly at the same time. The D flip-flop requires a minimum setup time for a level change at the D input to be recognized, so changes in the data level may not be recognized at the correct time. The probability of these marginal events may be extremely rare and perhaps go unnoticed. Data transmission protocols have been developed to detect such errors (parity checks, Hamming codes, etc.), so corrupted data can be rejected. However, in complex systems the combination of “glitches” can make the system “hang up”, necessitating a system reset.

Some key aspects of logic systems can be understood by inspecting the circuit elements that are used to form logic functions. Figure 5.4 shows simple inverter circuits using MOS transistors. These devices will be described in the next chapter. At this point it is sufficient to know that in an NMOS transistor a conductive (p.193)

Fig. 5.3 Some common logic symbols. Inverted outputs are denoted by small circles or by a superimposed bar, as for the latch output Q. Additional inputs can be added to gates as needed. An R-S flip-flop sets the Q output high in response to an S input. An R input resets the Q output to low.

channel is formed when the input electrode is biased positive with respect to the channel. The input, called the “Gate” (G), is capacitively coupled to the output channel connected between the “Drain” (D) and “Source” (S) electrodes. In the NMOS inverter applying a positive voltage to the gate makes the output channel conduct, so the output level is low. A PMOS transistor is the complementary device, where a conductive channel is formed when the gate is biased negative with respect to the source. Since the source is at positive potential, a low level at the inverter input yields a high level at the output. Regardless of the device and pulse polarity, the output pulse is always the inverse of the input. NMOS and PMOS inverters draw current when in their “active” state. Combining NMOS and PMOS transistors in a complementary MOS (CMOS) circuit allows zero current draw in both the high and low states with a substantial reduction in power consumption. A CMOS inverter is shown in Figure 5.5, which also shows how devices are combined to form a CMOS NAND gate. In the inverter the lower (NMOS) transistor is turned off when the input is low, but the upper (PMOS) transistor is turned on, so the output is connected to V DD, taking the output

Fig. 5.4 In an NMOS inverter the transistor conducts when the input is high (left), whereas in a PMOS inverter the transistor conducts when the input is low (right). In both circuits the input pulse is inverted, whether the input swings high or low.

(p.194)

Fig. 5.5 A CMOS inverter (left) and NAND gate (right).

high. Since the current path from V DD to ground is blocked by either the NMOS or PMOS device being off, the power dissipation is zero in both the high and low states. Current only flows during the level transition when both devices are on as the input level is at approximately V DD/2. As a result, the power dissipation of CMOS logic is significantly less than in NMOS or PMOS circuitry. As will be discussed in the next chapter, the reduction in power only obtains in logic circuitry. CMOS analog amplifiers are not fundamentally more power efficient than NMOS or PMOS circuits, although CMOS allows more efficient circuit topologies.

## 5.1.2 Propagation delays and power dissipation

Logic elements always operate in conjunction with other circuits, as illustrated in Figure 5.6. The wiring resistance in conjunction with the total load capacitance increases the rise time of the logic pulse and as a result delays the time when

Fig. 5.6 The wiring resistance together with the distributed load capacitance delays the signal.

(p.195) the transition crosses the logic threshold. The energy dissipated in the wiring resistance R is
(5.2)
$Display mathematics$
The current flow during one transition
(5.3)
$Display mathematics$
so the dissipated energy per transition (either positive or negative)
(5.4)
$Display mathematics$
If transitions occur at a frequency f, the power dissipation
(5.5)
$Display mathematics$
Thus, the power dissipation increases with clock frequency and the square of the logic swing.

Fast logic is time-critical. It relies on logic operations from multiple paths coming together at the right time. Valid results depend on maintaining minimum allowable overlaps (e.g. AND) and setup times (latches). Each logic circuit has a finite propagation delay, which depends on circuit loading, i.e. how many loads the circuit has to drive. In addition, as illustrated in Figure 5.6 the wiring resistance and capacitive loads introduces delay. This depends on the number of circuits connected to a wire or trace, the length of the trace and the dielectric constant of the substrate material. Relying on control of circuit and wiring delays to maintain timing requires great care, as it depends on circuit variations and temperature. In principle all of this can be simulated, but in complex systems there are too many combinations to test every one. A more robust solution is to use synchronous systems, where the timing of all transitions is determined by a master clock. Generally, this does not provide the utmost speed and requires some additional circuitry, but increases reliability. Nevertheless, clever designers frequently utilize asynchronous logic. Sometimes it succeeds … and sometimes it doesn't.

## 5.1.3 Logic arrays

Commodity integrated circuits with basic logic blocks are readily available, e.g. with four NAND gates or two flip-flops in one package. These can be combined to form simple digital systems. However, complex logic systems are no longer designed using individual gates. Instead, logic functions are described in a high-level language (e.g. VHDL), synthesized using design libraries, and implemented as custom ICs – “ASICs” (application specific ICs) – or programmable logic arrays. In these implementations the digital circuitry no longer appears as an (p.196)

Fig. 5.7 Complex logic circuits are commonly implemented using logic arrays that as an integrated block provide the desired outputs in response to specific input combinations.

ensemble of inverters, gates, and flip-flops, but as an integrated logic block that provides specific outputs in response to various input combinations. This is illustrated in Figure 5.7. Field Programmable Gate or logic Arrays (FPGAs) are a common example. A representative FPGA has 512 pads usable for inputs and outputs, ∼ 106 gates, and ∼ 100K of memory. Modern design tools also account for propagation delays, wiring lengths, loads, and temperature dependence. The design software also generates “test vectors” that can be used to test finished parts. Properly implemented, complex digital designs can succeed on the first pass, whether as ASICs or as logic or gate arrays.

# 5.2 Digitization of pulse height and time

For data storage and subsequent analysis the analog signal at the shaper output must be digitized. Important parameters for analog-to-digital converters (ADCs or A/Ds) used in detector systems are:

1. 1. Resolution: The “granularity” of the digitized output.

2. 2. Differential nonlinearity: How uniform are the digitization increments?

3. 3. Integral nonlinearity: How much does the relationship of the digital output to the analog input deviate from strict proportionality?

4. 4. Conversion time: How much time is required to convert an analog signal to a digital output?

5. 5. Count-rate performance: How quickly can a new conversion commence after completion of a prior one without introducing deleterious artifacts?

6. 6. Stability: Do the conversion parameters change with time?

Instrumentation ADCs used in industrial data acquisition and control systems share most of these requirements. However, detector systems place greater emphasis on differential nonlinearity and count-rate performance. The latter is important, as detector signals often occur randomly, in contrast to systems where signals are sampled at regular intervals. As in amplifiers, if the DC gain is not precisely equal to the high-frequency gain, the baseline will shift. Furthermore, following each pulse it takes some time for the baseline to return to its quiescent level. For periodic signals of roughly equal amplitude these baseline deviations (p.197) will be the same for each pulse, but for a random sequence of pulse with varying amplitudes, the instantaneous baseline level will be different for each pulse and affect the peak amplitude.

## 5.2.1 ADC parameters

### 5.2.1.1 Digitizer resolution

Digitization incurs approximation, as a continuous signal distribution is transformed into a discrete set of values. To reduce the additional errors (noise) introduced by digitization, the discrete digital steps must correspond to a sufficiently small analog increment. For an accurate measurement, the resolution of the ADC must be significantly better than the noise level of the signal. Since pulse amplitudes varying within the digitization interval ΔV yield the same digitization result, the rms error

(5.6)
$Display mathematics$
or for an ADC with a full scale range V and n-bit resolution
(5.7)
$Display mathematics$
This digitization noise must be smaller than the noise level of the analog input.

Another consideration is settling time. Given a single pole response V(t) = V 0 exp(−t/τ), for a given precision ΔV/V 0 the settling time t = − τ log (ΔV/V 0). To achieve a precision of 10−4 one must wait 9.2τ before acquiring the signal.

Apart from these considerations, the simplistic assumption is that the number of output bits n determines the digitizer resolution, ΔV = V/2n. For example, 13 bits yield ΔV/V = 1/8192 = 1.2 · 10−4.

If we plot the probability vs. pulse amplitude that a pulse height corresponding to a specific output bin is actually converted to that address or bin, an ideal ADC would show the response illustrated in Figure 5.8. In reality, the channel profile is not rectangular as sketched above. Assigning analog amplitudes to digital bins involves a threshold comparator. As in every amplitude measurement,

Fig. 5.8 Ideal ADC channel profiles.

(p.198)

Fig. 5.9 Measured channel profile of a 13-bit ADC.

the accuracy of the threshold discrimination is subject to electronic noise. As a result, the edges of the channel profile will be “smeared” by electronic noise in the digitizer circuitry. Figure 5.9 shows the measured channel profile of a high-quality 13-bit ADC. In this example about 70% of the events within the channel boundaries are actually converted into the correct bin. The profiles of adjacent channels overlap, as shown in Figure 5.10.

These channel profiles were measured by scanning a precision pulser across a channel and recording the fraction of pulses converted into the proper digital bin. However, channel profile can be checked quickly by applying the output of a precision pulser to the ADC and carefully adjusting the output amplitude to the center of a digital bin. If the pulser output has very low noise, i.e. the amplitude jitter is much smaller than the voltage increment corresponding to one ADC channel, nearly all pulses will be converted to a single channel, with only a small fraction appearing in the neighbor channels. However, this is only true for well-designed ADCs. Figure 5.11 shows results from an ADC whose digital resolution is better than its analog resolution. In the 13-bit range the pulser

Fig. 5.10 The channel profiles of adjacent channel overlap.

(p.199)

Fig. 5.11 Spectrum of a precision pulser centered within an ADC channel. The maximum number of counts per channel is about 106. In the 13-bit range (left) the signal is distributed over many channels. In the 11-bit range the spectrum is matches the digital resolution. Although this ADC can provide 13 bits of digital resolution, its analog resolution is only 10 – 11 bits.

signal is distributed over > 12 channels, whereas in the 11-bit range the digital resolution matches the analog resolution. Although this ADC can provide 13 bits of digital resolution, its analog resolution is only 10 – 11 bits, so the 12th and 13th bits are superfluous.

How much ADC resolution is required? If all counts of a peak fall in one bin, the resolution is ΔV. If the counts are distributed over several bins, peak fitting can yield substantially better resolution, depending on statistics. Figure 5.12 shows a signal with a constant width digitized with bin widths of ΔV = 2σ, σ, 0.5σ, and 0.25σ. Fitting can determine the centroid position to a fraction of the bin width even with coarse digitization, if only one peak is present and the line shape is known. Five digitizing channels within a linewidth (FWHM) allow robust peak fitting and centroid finding, even for imperfectly known line shapes and overlapping peaks.

### 5.2.1.2 Differential nonlinearity

Differential nonlinearity (DNL) is a measure of the uniformity of channel profiles over the range of the ADC. Depending on the nature of the distribution, either a peak or an rms specification may be appropriate:

(5.8)
$Display mathematics$
where 〈ΔV〉 is the average channel width and ΔV(i) is the width of an individual channel.

Differential nonlinearity of < ± 1% max. is typical, but state-of-the-art ADCs can achieve 10−3 rms, i.e. the variation is comparable to the statistical fluctuation for 106 random counts. Instrumentation ADCs are often specified with an (p.200)

Fig. 5.12 Digitized spectra of a Gaussian peak whose width σ = 1. ADC resolution Δ V is increased by factors of two from 2σ (top left) to 0.25σ (bottom right).

accuracy of ± 0.5 LSB (least significant bit) or greater, so the differential nonlinearity may be 50% or more. If the differential nonlinearity exceeds ± 0.5 LSB, the conversion can be nonmonotonic. For certain analog values an increase in signal will lead to a decreased digitized result. Figure 5.13 shows some typical plots of differential nonlinearity, both with a suppressed zero, so that the DNL is visible. The signal spectrum was “white” and is a section of the Compton continuum

Fig. 5.13 Response of two ADC to a “white” spectrum, both vertical scales with suppressed zeros. The left-hand plot shows a random DNL distribution, whereas the right-hand plot (with 1/10 vertical scale) shows pronounced periodic structures.

(p.201)

Fig. 5.14 Integral nonlinearity measurement on a 13-bit ADC. Left the digitized output is plotted vs. input amplitude. The right-hand plot shows the deviation of the digitized output from a straight-line fit.

from a plastic scintillator, so the spectrum is smooth. Sufficient counts were accumulated so that the statistical deviations were much smaller than the DNL. The left hand plot shows a random distribution of DNL, whereas the right hand plot shows periodic structures in the DNL. Poor ADC designs often show an odd-even effect, where the widths of alternating bins differ systematically.

### 5.2.1.3 Integral nonlinearity

Integral nonlinearity measures the deviation from proportionality of the measured amplitude to the input signal level. Figure 5.14 shows the channel number vs. input amplitude and the deviation of the output from a straight-line fit.

The linearity of an ADC depends on the input pulse shape and duration, due to bandwidth limitations in the circuitry. The integral nonlinearity shown above

Fig. 5.15 Integral nonlinearity measured with a 3 µs wide pulse, instead of the 400 ns pulse width used in Figure 5.14.

(p.202) was measured with a 400 ns wide input pulse. Increasing the pulse width to 3 µs improved the result significantly, as shown in Figure 5.15.

### 5.2.1.4 Conversion time

During the digitization of a signal the system cannot accept a subsequent signal (“dead time”). The dead time results from several successive steps in the conversion process:

1. 1. Signal acquisition time, which equals the time-to-peak plus settling time.

2. 2. Conversion time, which can depend on pulse height.

3. 3. Readout time to memory, which depends on speed of data transmission, buffer memory access and writing to mass storage.

In pulsed beam experiments dead time can be ignored if it is smaller than the pulse rate, so that conversion and data storage are complete before the next event. However, in continuous event streams, unless the event rate is very low, the measurement of yields or reaction cross-sections requires a measurement of dead time, e.g. with a reference pulser fed simultaneously into the spectrum. The total number of reference pulses issued during the measurement is counted and compared with the number of pulses recorded in the spectrum.

As will be seen below, the conversion time can depend on the pulse height. Does this mean that the efficiency is a function of pulse height? Usually not. If events in different parts of the spectrum are not correlated in time, i.e. random, they are all subject to the same average dead time (although this average will depend on the spectral distribution). However, be cautious when events are correlated. For example, in decay chains where the lifetime is less than the dead time, the daughter decay will be lost systematically.

### 5.2.1.5 Count rate effects

Circuitry in ADCs is mostly analog, so as in amplifiers one often encounters internal baseline shifts with event rate or undershoots following a pulse. If signals occur at constant intervals, the effect of an undershoot

Fig. 5.16 Centroid shift vs. pulse rate of two 13-bit ADCs (8192 channels).

(p.203) will always be the same. However, in a random sequence of pulses, the effect will vary from pulse to pulse, which leads to spectral broadening. Baseline shifts tend to manifest themselves as a systematic shift in centroid position with event rate. Measured results for two 13-bit ADCs subjected to a random rate are shown in Figure 5.16. At rates approaching 4 · 104 s−1 the centroid shift of the inferior unit is sufficiently large to cause significant resolution degradation.

### 5.2.1.6 Stability

The conversion gain and baseline are subject to change with time and temperature. Stability vs. temperature is usually adequate with modern electronics in a laboratory environment, especially since temperature changes within an enclosure or integrated circuit are typically much smaller than ambient changes. However, in highly precise or long-term measurements one should monitor changes in gain and baseline of the overall system. A simple technique is to inject precision reference pulses to place a reference peak at both the low and high end of the spectrum. The difference between the two peaks yields the gain, and the position of either peak then determines the offset.

## 5.2.2 Analog-to-digital conversion techniques

Analog-to-digital converters suitable for the digitization of individual pulses tend to use variations of a few basic techniques. Here we just review some basic conversion principles to illustrate the strengths and weaknesses of different conversion techniques. Analog-to-digital converters are key components in many applications, so a wealth of literature can be found on the world wide web. Application

Fig. 5.17 Block diagram of a flash ADC.

(p.204)

Fig. 5.18 Principle of a successive approximation ADC. The DAC is controlled to sequentially add levels proportional to 2n, 2n−1, … 20. The corresponding bit is set if the comparator output is high (DAC output < pulse height).

notes from major integrated circuit houses are a good source. Horowitz and Hill (1989) also discuss ADC techniques.

### 5.2.2.1 Flash ADC

Conceptually, the simplest technique is flash conversion, illustrated in Figure 5.17. The signal is fed in parallel to a bank of threshold comparators. The individual threshold levels are set by a resistive divider. The comparator outputs are encoded such that the output of the highest level comparator that fires yields the correct bit pattern. The threshold levels can be set to provide a linear conversion characteristic where each bit corresponds to the same analog increment, or a nonlinear characteristic, to provide increments proportional to the absolute level, which provides constant relative resolution over the range.

The big advantage of this scheme is speed; conversion proceeds in one step and conversion times < 10 ns are readily achievable. The drawbacks are component count and power consumption, as one comparator is required per bit. For example, an eight-bit converter requires 256 comparators. The conversion is always monotonic and differential nonlinearity is determined by the matching of the resistors in the threshold divider. Only relative matching is required, so this topology is a good match for monolithic integrated circuits. Flash ADCs are available with conversion rates > 500 MS/s (megasamples per second) at eight-bit resolution. The power dissipation is about 5 W. A practical issue is the high input capacitance of many comparator inputs in parallel, so the driver must have sufficient current drive capability to charge up this capacitance commensurate with the fast conversion time. The required settling time increases the conversion time at high resolution, as V = V 0 (1 − e t), so for the signal to approach its peak value to a precision of 10−3 requires a time of seven time constants τ.

### 5.2.2.2 Successive approximation ADC

The most commonly used technique is the successive approximation ADC, shown in Figure 5.18. The input pulse is sent (p.205)

Fig. 5.19 A correction DAC can be used to improve differential nonlinearity.

to a pulse stretcher, which follows the signal until it reaches its cusp and then holds the peak value. The stretcher output feeds a comparator, whose reference is provided by a digital-to-analog converter (DAC). The DAC is cycled beginning with the most significant bits. The corresponding bit is set when the comparator fires, i.e. the DAC output becomes less than the pulse height. Then the DAC cycles through the less significant bits, always setting the corresponding bit when the comparator fires. Thus, n-bit resolution requires n steps and yields 2n bins. This technique makes efficient use of circuitry and is fairly fast. High-resolution devices (16 – 20 bits) with conversion times of order μs are readily available. Currently, a 16-bit ADC with a conversion time of 1 µs (1 MS/s) requires about 100 mW.

A common limitation is differential nonlinearity, since the resistors that set the DAC levels must be extremely accurate. For DNL < 1% the resistor determining the 212 level in a 13-bit ADC must be accurate to < 2.4 · 10−6. As a consequence, differential nonlinearity in high-resolution successive approximation converters is typically 10 – 20% and often exceeds the 0.5 LSB required to ensure monotonic response.

The differential nonlinearity can be corrected by various techniques. One is to average over many channel profiles for a given pulse amplitude, the “sliding scale” technique originated by Gatti (Cottini, Gatti, and Svelto 1963). Here an analog increment is added event-by-event and the digitized output is corrected accordingly. Thus, for a large number of events the conversion of a given pulse amplitude utilizes many states of the converter. For a random amplitude distribution this averages over many channel profiles and equalizes the differential (p.206) nonlinearity. When properly implemented this provides excellent differential nonlinearity with no significant degradation of the channel profile. However, flawed implementations are prone to step-like discontinuities in the DNL vs. amplitude.

Another technique is the “brute force” approach of using a correction DAC. The primary DAC output is adjusted by the output of a correction DAC to reduce differential nonlinearity. This is shown in Figure 5.19. Correction data are derived from a measurement of DNL. Corrections for each bit are loaded into the RAM, which acts as a lookup table. For each address of the main DAC the appropriate correction is applied to the correction DAC. The range of the correction DAC must exceed the peak-to-peak differential nonlinearity. If the correction DAC has N bits, the maximum DNL is reduced by 2−(N−1) (if the deviations are symmetrical).

### 5.2.2.3 Wilkinson ADC

The Wilkinson ADC (Wilkinson 1950) has traditionally been the mainstay of precision pulse digitization. The principle is shown in Figure 5.20. The peak signal amplitude V is acquired by a combined peak detector/pulse stretcher and transferred to a memory capacitor. The output of the peak detector initiates the conversion process:

1. 1. The memory capacitor is disconnected from the stretcher.

2. 2. A current source is switched on to linearly discharge the capacitor with current I R.

3. Fig. 5.20 Principle of a Wilkinson ADC. After the peak amplitude has been acquired, the output of the peak detector initiates the conversion process. The memory capacitor is discharged by a constant current while counting the clock pulses. When the capacitor is discharged to the baseline level V BL the comparator output goes low and the conversion is complete.

(p.207)
4. 3. Simultaneously with commencing the discharge a counter is enabled to determine the number of clock pulses until the voltage on the capacitor reaches the baseline level V BL.

The time required to discharge the capacitor is a linear function of pulse height,

(5.9)
$Display mathematics$
so the counter content provides the digitized pulse height. The clock pulses are provided by a crystal oscillator, so the time between pulses is extremely uniform and this circuit inherently provides excellent differential linearity. The drawback is the relatively long conversion time T C, which for a given resolution is proportional to the clock period T clk and the pulse height, T C = n × T clk (n = channel number ∝ pulse height). For example, a clock frequency of 100 MHz provides a clock period T clk = 10 ns and a maximum conversion time T C = 82 µs for 13 bits. Clock frequencies of 100 MHz are typical, but > 400 MHz have been implemented with excellent performance (DNL < 10−3). This scheme makes efficient use of circuitry and allows low power dissipation. Wilkinson ADCs have been implemented in 128-channel readout ICs for silicon strip detectors (Garcia-Sciveres et al. 1999). Each ADC added only 100 µm to the length of a channel and a power of 300 µW per channel (see Chapter 8).

Many important details are not shown in Figure 5.20. For example, the beginning of the discharge must be synchronized with the clock. Switching the current source requires some time, which introduces nonlinearity for small signals. Cross-talk from the clock or counter to the analog circuitry can introduce correlations into the differential nonlinearity, as illustrated in Figure 5.13. It is tempting to utilize both the leading and trailing edge of the clock pulse to double the clock frequency and reduce conversion time. However, the duty cycle of the clock pulse must be constrained very accurately to 50% to avoid degradation of differential nonlinearity. This technique typically leads to odd–even structures in the DNL, so the least significant bit can become unusable. Simply suppressing this bit also reduces the conversion time two-fold, so “clock doubling” becomes self-defeating.

### 5.2.2.4 Hybrid analog-to-digital converters

Conversion techniques can be combined to obtain high resolution and short conversion time. One example combines a flash ADC with a successive approximation or a Wilkinson (ramp run-down) converter. The fast flash ADC provides coarse conversion (e.g. 8 out of 13 bits) and the successive approximation or Wilkinson converter provides fine resolution. Since the second conversion range is small, the conversion time is significantly reduced. For example, a Wilkinson ADC covering 256 channels with a 100 MHz clock requires only 2.6 µs, which is comparable to a successive approximation ADC, but with superior differential nonlinearity.

Another approach is to use flash ADCs with sub-ranging. Not all applications require constant absolute resolution over the full range. Sometimes only relative (p.208)

Fig. 5.21 A 12-bit pipelined ADC. The first four stages have a 3-bit output, but only 2-bit resolution, so the first four stages provide 8 bits. The last stage is a flash ADC that provides the final 4 bits.

resolution must be maintained, especially in systems with a very large dynamic range.

Sub-ranging utilizes a precision binary divider at the input to determine the coarse range and a fast flash ADC for fine digitization. One example is a fast digitizer that fits in phototube base and provides 17 to 18 bit dynamic range with 16 ns conversion time (Yarema et al. 1993, Zimmerman and Hoff 2004). The converter provides a digital floating point output (4 bit exponent, 8+1 bit mantissa).

A popular architecture is the pipelined ADC, which consists of sequential conversion steps, as illustrated in Figure 5.21. The input to each stage is fed both to a sample and hold and a three-bit flash ADC. The sample and hold (S&H) maintains the signal level during conversion. The flash ADC quantizes its input to 3-bit accuracy. This output is fed to a DAC with 12-bit accuracy. The DAC's analog output is subtracted from the original signal and the difference signal is passed on to the next stage. The last 4 bits are resolved by a 4-bit flash ADC. As soon as a stage has passed its result to the next stage it can begin processing the next signal, so throughput is not determined by the total conversion time, but by the time per stage. Since outputs from individual stages appear sequentially, the outputs must be aligned in time to form the cumulative digitized output. Since the interstage gain is only four (rather than eight corresponding to 3 bits), each stage only contributes 2 bits of resolution. The extra bit is used for error correction. Commercially available pipelined ADCs provide 1 GS/s conversion rates with eight-bit resolution and a power dissipation of about 1.5 W. Note that (p.209)

Fig. 5.22 The simplest form of time digitizer counts the number of clock pulses between the start and stop signals.

the effective resolution at the maximum sampling rate is less than the digital resolution.

Other techniques, the sigma-delta ADC being a notable example, measure incremental changes over the waveform. This architecture is popular in audio applications, so the frequencies are much lower than needed for the digitization of detector pulses.

# 5.3 Time-to-digital converters (TDCs)

Measurements of time intervals can utilize digital and analog techniques.

## 5.3.1 Counter

The combination of a clock generator with a counter is the simplest technique, shown in Figure 5.22. The clock pulses are counted between the start and stop signals, which yields a direct readout in real time. The limitation is the speed of the counter, which in current technology is limited to about 1 GHz, yielding a time resolution of 1 ns. Using the stop pulse to strobe the instantaneous counter status into a register provides multi-hit capability.

## 5.3.2 Analog ramp

Analog techniques are commonly used in high-resolution digitizers to provide resolution in the range of ps to ns. The principle is to convert a time interval into a voltage by charging a capacitor through switchable current source. The start pulse turns on the current source and the stop pulse turns it off. The resulting voltage on the capacitor C is V = Q/C = I T (t stopt start)/C, which is digitized by an ADC. A convenient implementation switches the current source to a smaller discharge current I R and uses a Wilkinson ADC for digitization, as illustrated in Figure 5.23. This technique provides high resolution, but at the expense of dead time and multi-hit capability.

## 5.3.3 Digitizers with clock interpolation

Integrated circuit technology makes it practical to implement clock interpolation to provide ps resolution together with multi-hit capability and no dead time (p.210)

Fig. 5.23 Combining a time-to-amplitude converter with an ADC forms a time digitizer capable of ps resolution. The memory capacitor C is charged by the current I T for the duration T startT stop and subsequently discharged by a Wilkinson ADC.

(Arai and Ohsugi 1986, 1989). A block diagram is shown in Figure 5.24. The clock period is interpolated by inverter delays (U1, U2, …). The delay can be fine-tuned by adjusting the operating current of the inverters. This does not provide very tight control against temperature or voltage variations, so the delays are stabilized by a delay-locked loop referenced against the master clock, which is typically a very stable crystal oscillator, as indicated at the bottom of Figure 5.24 (Arai et al. 1998). The delay-locked loop ensures that the total delay of the interpolation chain is an integer multiple of the clock period. Devices with 250 ps resolution have been fabricated and tested for use in high-energy physics experiments, but the technique should be applicable to higher resolution digitizers.

# 5.4 Digital signal processing

Up to now we have utilized analog techniques for pulse shaping. However, filtering can also be applied in the digital domain. This is a topic worthy of a book in itself, so this will only be a brief introduction designed to provide some perspective relevant to large-scale detector systems. For a more detailed discussion of digital signal processing techniques see texts by Ifeachor and Jervis (1993), Oppenheimer and Schafer (1998), and others. For examples applied to detector pulse processing see Pullia et al. (2000) and Cardoso et al. (2004), which also give additional references.

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Fig. 5.24 Time digitizer using clock interpolation. The interpolator delays are controlled by a delay-locked loop referenced to the master clock oscillator (Arai et al. 1998).

First, the detector signal is sampled with a fast digitizer with sufficient resolution to reconstruct the pulse, as shown in Figure 5.25. Subsequently, a digital signal processor (DSP) applies the appropriate algorithms to filter the pulse and extract the pulse height (Figure 5.26). Digital signal processing allows great flexibility in implementing filtering functions. The software can be changed readily to adapt to a wide variety of operating conditions and it is possible to implement filters that are impractical or even impossible using analog circuitry. However, this comes at the expense of increased circuit complexity and increased demands on the ADC compared to analog shaping.

Fig. 5.25 Sampling a pulse to allow digital signal processing. The pulse shown is the current pulse from a strip detector.

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Fig. 5.26 Block diagram of a detector readout using digital signal processing.

Figure 5.27 illustrates how a filter function can be implemented using digital techniques. The amplitude of the input signal is multiplied at each discrete time step by a filter weighting function. The filter function can be calculated in real time by the DSP or it can be stored as values in a look-up table. This process could be applied to either a continuous or a digitized input signal. Subsequently the samples are integrated. Since the amplitudes add coherently, whereas the noise components add in quadrature, this yields a net improvement in signal-to-noise ratio. It is also rather straightforward to show that the optimum signal-to-noise ratio obtains when the weighting function has the same shape as the input signal. This is an example of a “matched filter”. However this is only the optimum filter for retrieving the signal while retaining its shape. As we have seen, integrating the signal to extend its duration and then filtering decouples the choice of filter parameters from the original signal duration.

The simple scheme shown in Figure 5.27 requires that the time of the desired signals is known, so the weighting factors can be synchronized with the signal. This constraint is removed when the filtering is performed by convolution, so the DSP block in Figure 5.26 performs a sequence of multiplications and sums

Fig. 5.27 In a simple digital filter the input signal is multiplied at each discrete time step by a filter weighting function.

(p.213)
(5.10)
$Display mathematics$
where S o and S i are the output and input signals and W is the weighting function that yields the desired pulse shape. This is analogous to pulse shaping in analog systems (eqn 4.1). In digital signal processing this is referred to as a finite impulse response (FIR) filter, similar to an infinite impulse response (IIR) filter, which takes the sum to infinity. Specialized digital signal processors optimized to perform these functions are available, but FPGAs also allow very efficient implementations. Without special hardware algorithms can be tested on a desktop computer using realistic detector pulses and noise spectra to assess artifacts in the output spectrum, for example using C++ functions (Embree and Danieli 1999).

The sample interval must be sufficiently small to capture the pulse structure. Figure 5.28 shows the same pulse as in Figure 5.25, but sampled at intervals of 4 ns instead of 1 ns. The sampling interval of 4 ns misses the initial peak.

This illustrates the Nyquist criterion. The ADC must digitize at greater than twice the rate of the highest frequency component in the signal. Apart from missing information on the fast components of the pulse, undersampling introduces spurious artifacts. With too low a sampling rate high frequency components will be “aliased” to lower frequencies, as shown in Figure 5.29.

To prevent aliasing, a low-pass filter must be introduced before the ADC. As a result, an additional analog block must be added to the signal processing chain (Figure 5.30). When an input frequency f i is sampled at a rate f s, the output frequencies can be reconstructed as f i ± kf s, where k is any integer value. Thus, the input is aliased to both lower and higher frequencies and the prefilter (“anti-aliasing filter”) is needed to exclude both possibilities. Every sampling process is subject to aliasing – e.g. also 2D or 3D image processing.

Fig. 5.28 Sampling at too low a rate does not preserve the full pulse structure.

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Fig. 5.29 Sampling at too low a rate “aliases” a frequency components to lower frequencies.

The preamplifier is necessary to raise the level of the input noise sources such that the digitization noise of the ADC is negligible. As already noted in Section 5.2.1.1, the signal quantization inherent to the digitization process introduces quasi-random noise

(5.11)
$Display mathematics$
where ΔV is the signal increment corresponding to one bit. This quantization noise is increased by differential nonlinearity. When the Nyquist condition is fulfilled the noise is spread nearly uniformly and extends to 1/2 the sampling frequency f S, so the spectral noise density
(5.12)
$Display mathematics$
Sampling at a higher frequency spreads the total noise over a larger frequency range, so oversampling can be used to increase the effective resolution.

From this we see that the front-end electronics and ADC must exhibit the same precision as in an analog system, i.e. the baseline and other pulse-to-pulse amplitude fluctuations must be less than order Q n/10, i.e. typically 10−4 in high-resolution systems. For 10 V full scale at the ADC input in a high-resolution gamma-ray detector system, this corresponds to < 1 mV. In practice the effective

Fig. 5.30 A low-pass filter (prefilter) inserted in the ADC input prevents aliasing of high-frequency components into the desired frequency range.

(p.215) resolution of ADCs suitable for these applications is commonly 2 bits worse than nominal, so this must be taken into account. At very high resolution the electronic noise of the ADC's input circuitry becomes the limit. For example, in a 24-bit ADC with a full-scale range of 10 V one bit corresponds to a voltage difference of 0.4 nV. The thermal noise of a 50 Ω resistor in 1 Hz bandwidth is more than twice as large. Furthermore, the dynamic range requirements for ADC may be more severe than in an analog filtered system, as can be seen from the rather high peak-to-average ratio of the pulse in Figure 5.25. In any case, the ADC must provide high performance at short conversion times.

Today digital signal processing is technically feasible for some applications, e.g. detectors with moderate to long collection times (gamma and x-ray detectors), and systems are commercially available. Nevertheless, these systems tend to be complex and power-hungry.

In large-scale systems, however, the benefits are not so clear. Where intimate integration of sensors and electronics in a small volume is required, both circuit area and power dissipation are crucial considerations. Furthermore, these are special purpose systems. The electronics are specifically tailored to the sensor and application and do not need to be modified during the course of the experiments (the inevitable upgrades notwithstanding). Furthermore, simple analog filters usually provide results that are only slightly inferior to the optimized filters that a DSP system would allow.

The benefits of digital signal processing are:

1. 1. Flexibility in implementing filter functions.

2. 2. Filters are possible that are impractical in hardware.

3. 3. Filter parameters can be changed simply.

4. 4. Tail cancellation and pile-up rejection are easily incorporated.

5. 5. Adaptive filtering can be used to compensate for pulse shape variations.

Where is digital signal processing appropriate? It provides clear benefits in systems that are highly optimized for resolution, high counting rates, and variable sensor pulse shapes.

Where is analog signal processing best (most efficient)? In systems that require fast time response the high power requirements of high-speed ADCs are prohibitive. Systems that are not sensitive to pulse shape can use fixed shaper constants and rather simple filters, which can be either continuous or sampled. For example, the APV25 chip described in Chapter 8 applies discrete sample processing using analog circuitry. Finally, in high density systems that require small circuit area and low power, analog filtering can efficiently transpose the relevant information to a frequency domain where digitization requirements are less demanding.

Given the dearth of good analog circuit designers and no prospects for improvement, it is often claimed that digital signal processing is a better match to available skills and avoids the need to understand the wide range of details that a sophisticated analog system requires. This argument is specious; both types (p.216) of systems require careful analog design. Nevertheless, progress in fast ADCs (precision, reduced power) will expand the range of DSP applications.

References

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Arai, Y. and Ohsugi, T. (1989). TMC – a CMOS time to digital converter VLSI. IEEE Trans. Nucl. Sci. NS-36/1 (1989) 528–531

Arai, Y. et al. (1998). Time memory cell VLSI for the PHENIX drift chamber. IEEE Trans. Nucl. Sci. NS-45/3 (1998) 735–739 and references therein.

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